Publications , White Papers , Talks and Patents

Publications:

[YWF87]

Yen, C., R. Walker and B. McFarland, Delay Calculation for Emitter-Coupled Logic Gates - How Fast is HP1X Process?, Proceedings of the Hewlett-Packard 1987 VLSI Design Technology Conference, May 18-20, 1987, S10.3.1-8.

[WSM87] [clean paper (no figures)] [scanned paper w/figures)]

Walker, R., W. McFarland, C. Stout, C. Yen, A 46 I/O Package for Prototyping Multi-GHz Circuits, 1987 HPL Internal Report.

[Wal87] [paper] [figs1] [figs2] [scanned paper w/figs]

Walker, R., A Monolithic High-Speed Voltage Controlled Ring Oscillator , Proceedings of the Hewlett-Packard 1987 VLSI Design Technology Conference, May 18-20, 1987, S10.6.1-5.

[CKM88] [paper]

Colinge, J. P., J. Kang, W. McFarland, C. Stout and R. Walker, Evaluation Results For Several High-Speed SOI CMOS Circuits, Proceedings of the Hewlett-Packard 1988 VLSI Design Technology Conference, May 23-25, 1988, 356-363.

[Wal88]

Walker, R., A Monolithic Clock Extraction and Retiming Circuit for Gigahertz Rate Data Links , Proceedings of the Hewlett-Packard 1988 VLSI Design Technology Conference, May 23-25, 1988, 279.

[WPS89] [paper]

Walker, R., K. Poulton, C. Stout, B. McFarland and J. Kang, Circuit Optimization Using the Simplex Algorithm, Proceedings of the Hewlett-Packard 1989 VLSI Design Technology Conference, May 22-24, 1989, 390-397.

[WHY89] [paper]

Walker, R. C., T. Hornak, C. Yen and K. Springer, A Chipset for Gigabit Rate Data Communication, Proceedings of the 1989 Bipolar Circuits and Technology Meeting, September 18-19, 1989, 288- 290.

[WHY90] [scanned paper]

Walker, R. C., T. Hornak, C. Yen, J. Doernberg and K. Springer, A 1.5 Gb/s Link Interface Chipset For Computer Data Transmission, HP Laboratories Technical Report HPL-90-105(July 1990).

[LaW90]

Lai, B. and R. Walker, A Monolithic 622 MBit/s Clock Extraction Data Retiming Circuit, Proceedings of the Hewlett-Packard 1990 VLSI Design Technology Conference, May 22-25, 1990, 237-244.

[DMW91]

Doernberg, J., W. McFarland, R. C. Walker and T. A. Knotts, Rapid Techniques to Beat the Competition, An 8-week, 1.5 Gwords/s, PRWS IC Design, Proceedings of the Hewlett-Packard 1991 VLSI Design Technology Conference, May 21-24, 1991 , 249-256.

[LaW91] [paper]

Lai, B. and R. Walker, A Monolithic 622 MBit/s Clock-Extraction Data Retiming Circuit, ISSCC Digest of Technical Papers 34 (February 13-15, 1991), 144-145.

[WHY91] [paper]

Walker, R. C., T. Hornak, C. Yen, J. Doernberg and K. H. Springer, A 1.5 Gb/s Link Interface Chipset For Computer Data Transmission, IEEE Journal on Selected Areas in Communications 9, 5 (June 1991).

[Wal92a] [thesis]

Walker, R. C., The Design and Implementation of a Chipset for Gigabit/Second Computer Networks, Graduate Thesis for Master of Science in Computer Science, California State University, Chico CA. Summer 1992, 1-51.

[Wal92b] [scanned paper]

Walker, R. C., Bang-Bang Loop Analysis, Hewlett- Packard Journal, October 1992, 110.

[WWS92] [paper]

Walker, R., J. Wu, C. Stout, B. Lai, C. Yen, T. Hornak and P. Petruno, A 2-Chip 1.5Gb/s Bus- Oriented Serial Link Interface, ISSCC Digest of Technical Papers 35(February 19-21, 1992).

[WSL92]

Walker, R., C. Stout, B. Lai, C. Yen, T. Hornak and P. Petruno, A 2-Chip 1.5Gb/s Bus-Oriented Serial Link Interface , Proceedings of the Hewlett-Packard 1992 VLSI Design Technology Conference, May 19-22, 1992, 85-91.

[WSW92] [paper]

Walker, R. C., C. L. Stout, J. Wu, B. Lai, C. Yen, T. Hornak and P. T. Petruno, A 2-Chip 1.5 Gigabaud Serial Link Interface, IEEE Journal of Solid State Circuits 27, 12 (December 1992), 1805-1.

[LaW92]

Lai, B. and R. C. Walker, Monolithic Chip Retimes Data at 622 Mb/s, Microwaves & RF, March 1992, 202-205.

[MWS92] [paper]

McFarland, W., R. Walker, C. Stout, J. Wu, B. Lai, G. Kwan and C. Yen, HP's Link Interface Chipset for Serial-HIPPI, Compcon Proceedings, February 24-28, 1992.

[YWP92] [scanned paper]

Yen, C., R. C. Walker, P. T. Petruno, C. Stout, B. W. H. Lai and W. J. McFarland, G-Link: A Chipset for Gigabit-Rate Data Communication, Hewlett- Packard Journal, October 1992, 103-109, 111-116.

[YWM92] [paper]

Yen, C., R. Walker, W. McFarland, D. Cunningham, G. Kwan, T. Hornak, Serial Extension for 800/1600 Mb/s Computer Interconnect , Supercomm ICC 14-18 June, 1992, 981-4 vol.2.

[YWS92] [paper]

Yen, C., R. Walker, C. Stout, B. Lai, J. Wu, A General Purpose Link Interface Chipset for Gigabit Rate Data Communication, IEEE Conference 6-9 Dec. 1992, 197-200 vol.1

[TeW92] [paper]

Teetzel, A. and R. Walker, A GaAs IC Broadband Variable Ring Oscillator and Arbitrary Integer Divider , Trans. MTT Symposium, December 1992.

[WuW92] [paper]

Wu, J. and R. C. Walker, A Bipolar 1.5 Gb/s Monolithic Phase-Locked Loop for Clock and Data Extraction, Symposium on VLSI Circuits Digest of Technical Papers, June 1992, pp. 70-71.

[HGM93]

Hornak, T., A. Grzegorek, B. McFarland, R. Walker, S. Willingham Image Rejection Improvements in Superheterodyne Radio Receivers by Time Sharing, HP Laboratories Technical Report, HPL-93-53, June, 1993, pp 1-56.

[WFW93] [paper]

Wuppermann, B., B. Fox, R. Walker, S. Atkinson, D. Budin, C. Lanzl and S. Bleiweiss, A 16-PSK Modulator with Phase Error Correction , ISSCC Digest of Technical Papers 36, 27 (February 24-25 1993), 138-139.

[HMW94]

Hornak, T., B. McFarland, R. Walker Quadrature Mixers with Improved Gain Matching and Single Phase Local Oscillator Signal, HP Laboratories Technical Report, HPL-94-80, August, 1994, pp 1-56.

[WSY97] [paper]

Walker, R. C., C. Stout, C. Yen and L. R. Dove, A 2.488-Gbit/s Silicon Bipolar Clock and Data Recovery Circuit for SONET Fiber-Optic Communications Networks , Hewlett-Packard Journal, December 1997, 111-119.

[WSY97a] [paper] [pdf slides]

Walker, R.C., C. Stout, C. Yen, 2.488 Gb/s Si-Bipolar Clock and Data Recovery IC with Robust Loss of Signal Detection, ISSCC Digest of Technical Papers 40 (February 1997), 246,247,466.

[WSY97b] [paper]

Yen, R. W. C. S. C., A 2.488 Gb/s Si-Bipolar Clock and Data Recovery IC with Robust Loss of Signal Detection, HP Design Conference Digest of Technical Papers 40(May 23, 1997).

[WHK98] [paper] [pdf slides]

Walker, R. C., K. Hsieh, T. A. Knotts and C. Yen, A 10Gb/s Si-Bipolar TX/RX Chipset for Computer Data Transmission , ISSCC Digest of Technical Papers 41(February 1998), 302,303,450.

[Wal03] [preprint]

Walker, R.C., Designing Bang-bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems, pp. 34-45, a chapter appearing in "Phase-Locking in High-Performance Sytems - From Devices to Architectures", edited by Behzad Razavi, IEEE Press, 2003, ISBN 0-471-44727-7.

White Papers:

[Wal00]

Walker, R., "A monolithic calibration technique for precise multi-phase clock generation", Agilent Labs Patent Disclosure, February 25, 2000. (See patent application [Wal03c], below)

[Wal01a]

Walker, R., "A tuneable 40Gb/s CDR with jitter stimulus/response designed for fast-track implementation in Agilent test equipment (draft)", Agilent Labs Internal Memo, May 23, 2001.

Talks:

Tutorials and Short Courses

[Wal97]

Walker, R., Clock and Data Recovery for Serial Data Communications, ISSCC Tutorial, February 1997. (Wal98, Wal02a are successively updated versions).

[Wal98] [cdr checklist and references]

Walker, R., Clock and Data Recovery for Serial Data Communications (with a tutorial on Bang-Bang Loop design), BCTM Tutorial, September 27 1998. (Wal02a is an updated version).

[Wal02a] [mp3 audio file (40Meg)]

Walker, R. C. Clock and Data Recovery for Serial Data Communications, focussing on bang-bang CDR design methodology, ISSCC Short Course, February 2002.

IEEE802.3 10 Gigabit Ethernet Presentations

[Wal99b]

R. C. Walker, 10GbE over coaxial cable, prepared for IEEE 802.3 High Speed Study Group, July 6-7, 1999, Montreal, PQ.

[WaD99]

R. C. Walker, R. Dugan Low overhead coding proposal for 10Gb/s serial links, IEEE 802.3 High Speed Study Group, November 9-10, 1999, Kauai, HI. http://grouper.ieee.org/groups/802/3/ 10G_study/public/nov99/walker_1_1199.pdf

[WaD00]

R. C. Walker, R. Dugan 64b/66b low-overhead coding proposal for serial links, IEEE 802.3 High Speed Study Group, January 18-20, 2000 Dallas, TX. http://grouper.ieee.org/groups/802/3/10G_study/public/jan00/walker_1_0100.pdf

[WAK00]

Rick Walker, Birdy Amrutur, Tom Knotts, Richard Dugan, 64b/66b coding update, IEEE 802.3 High Speed Study Group, March 7-8, 2000, Albuquerque, NM. http://grouper.ieee.org/groups/802/3/ae/public/mar00/walker_1_0300.pdf

[WDA00]

Rick Walker, Richard Dugan, Birdy Amrutur, John Ewen, Rich Taborek, Don Alderrou, Howard Frazier, Paul Bottorff, Brad Booth, Kevin Daines, Osamu Ishida, 64b/66b PCS, 802.3 High Speed Study Group, May 23-25, 2000, Ottowa, Ontario, Canada. (Final presentation to IEEE as accepted for the "blue book" draft standard). http://grouper.ieee.org/groups/802/3/ae/public/may00/walker_1_0500.pdf

[ThW01]

Pat Thaler, Rick Walker An optimized self-test function for 64b/66b 802.3 High Speed Study Group, March 12, 2001, Hilton Head, South Carolina. http://grouper.ieee.org/groups/802/3/ae/public/mar01/thaler_1_0301.pdf

Optical Internetworking Forum Presentations

[WaD01]

R. C. Walker, R. Dugan, SFI-4 Phase 2 Interface using the 64b/66b Line Code Optical Internetworking Forum, Contribution OIF2001.586, November 6-8, 2001, Frisco, Texas.

[WDL02]

R. C. Walker, R. Dugan, Allan Lui SFI-4 Phase 2: 64b/66b Line Code Update Optical Internetworking Forum, Contribution OIF2002.018.00, January 28-30, 2002, San Diego, CA.

Industry trends

[Wal99]

R. C. Walker, Tb/s Chip I/O - how close are we to practical reality?, 10th Annual Workshop on Interconnections within High Speed Digital Systems, May 9-12, 1999, Santa Fe, New Mexico.

Philosophy

[Wal01 (pdf slides)] [mp3 audio file 14Meg]

Rick Walker, Conciousness, Communication and Cooperation - in brains, bodies, businesses and biospheres, A chalk talk presented at Agilent Labs, Palo Alto, CA, June 29, 2001. Present the philosophical underpinnings of, and a model of human conciousness based on quantum computation and eastern thought.

Patents:

[McW88]

McFarland, W. and R. C. Walker, Pseudo-Random Word Sequence Generator and Synchronizer, U.S. Patent (1) #4791653, December 13, 1988.

[Wal89]

Walker, R. C., A Fully Integrated High-Speed Voltage Controlled Ring Oscillator, U.S. Patent (2) #4884041, Nov. 28, 1989.

[CHN90]

Corsetto, C., T. Hornak, R. Nordby, R. C. Walker and C. Yen, Phase Locked Loop for Clock Extraction in Gigabit Rate Data Communication Links, U.S. Patent (3) #4926447, May 15, 1990.

[LaW91]

Lai, B. and R. C. Walker, Method and Apparatus for Clock Recovery and Data Retiming for Random NRZ data, United States Patent (4) #5012494, April 30, 1991.

[WaB91]

Walker, R. C. and H. Braun, Device to block unauthorized modem access over a PBX line, United States Patent (5) #5018190, May 21, 1991.

[CHH91]

Crandall, D., S. R. Hessel, T. Hornak, R. Nordby, K. H. Springer, C. Corsetto and R. C. Walker, DC- Free Line Code for Arbitrary Data Transmission, United States Patent (6) #5022051, June 4, 1991.

[DWM92]

Domokos, J., R. C. Walker and W. J. McFarland, High Frequency Common Mode Choke, United States Patent (7) #5138287, August 11, 1992.

[CHH95]

Crandall, D., S. R. Hessel, T. Hornak, R. Nordby, K. H. Springer, C. Corsetto and R. C. Walker, DC- Free Line Code for Arbitrary Data Transmission, United States Patent (8) #5438621, August 1, 1995.

[LaW96]

Lai, B. and R. C. Walker, Unity Gain Positive Feedback Integrator with Programmable Charging Currents, U.S. Patent (9) #5498992, March 12, 1996.

[HGM97]

Hornak, T., A. Z. Grzegorek, W. J. McFarland, R. C. Walker and S. D. Willingham, Modulation and Frequency Conversion by Time Sharing, United States Patent (10) #5678222, October 14, 1997.

[KSW98]

Knotts, T., Stout, C., Walker, R. C., Fully Integrated High-Speed Interleaved Voltage-Controlled Ring Oscillator, United States Patent (11) #5841325, November 24, 1998.

[WuW00]

Wu, Bin, R. C. Walker, Oversampling Rotational Frequency Detector, United States Patent (12) #6055286, April 25, 2000.

[BGW01]

Blalock, Travis, N. Gaddis, R. Walker, Analog pixel drive circuit for an electro-optical material-based display device, United States Patent (13) #6249269, June 19, 2001.

[WBG01]

Walker, Richard C., Travis N. Blalock, Neela B. Gaddis, Electro-optic material based display device having analog pixel drivers, United States Patent (14) #6329974, December 11, 2001.

[WAD01a]

Walker, Richard C., B. Amrutur, R. Dugan, Coding for packetized serial data, European Patent Application EP1133124A2, Sept. 12, 2001.

[WAD01b]

Walker, Richard C., B. Amrutur, R. Dugan, 64b/66b decoding for packetized serial data, European Patent Application EP1133123A2, Sept. 12, 2001.

[WMB01]

Walker, Richard C., P. Mertz, B. Bronson, K. Nishimura, Personal viewing device with system for providing information to a connected system, European Patent Application EP1132870A2, Sept. 12, 2001.

[Wal02b]

Walker, Richard C., Method and system for compensating for defects in a multi-light valve display system, United States Patent (15) #6359662. March 19, 2002.

[WAM01]

Walker, Richard C., Bharadwaj Amrutur, Peter Mottishaw, Steven C. Joiner, Larry A. Chesler, Ian Hardcastle, Network monitoring system with built-in monitoring data gathering, European Patent Application EP1152570A2, November 7, 2001.

[WaT01]

Walker, Richard C., Patricia A. Thaler, Data Communication System with Self-Test Function, European Patent Application EP1241823A1, March 6, 2002.

[WMT01]

Walker, Richard C., Pierre Mertz, Barclay J. Tullis, Immersive Display System, European Patent Application EP1152279A2, Sept. 12, 2001.

[HFW02]

Ho, Peter, Graham M. Flower, Richard C. Walker, Multiplexer with channel sectioning, selectively actuated current sources, and common-base amplifiers European Patent Application EPEP1187382a2, March 13, 2002.

[Wal02c]

Walker, Richard C., System and method for encoding an input data stream by utilizing a predictive, look-ahead feature, United States Patent (16) #6501404. December 31, 2002.

[Wal03b]

Walker, Richard C., Immersive Display System, United States Patent (17) #6552698. April 22, 2003.

[AmW03]

Amrutur, Bharadwaj S., Richard C. Walker, Serial communications system and method, European Patent Application EP1320208A2, September 30, 2002.

[Wal03c]

Walker, Richard C., Multi-phase sampling United States Patent Application #20030123591. July 3, 2003.

[WAD03d]

Walker, Richard C., B. Amrutur, R. Dugan, Decoding method and decoder for 64b/66b coded packetized serial data, United States Patent (18) #6650638. November 18, 2003.

[WAD04a]

Walker, Richard C., B. Amrutur, R. Dugan, Coding method and coder for packetized serial data with low overhead, United States Patent (19) #6718491. April 6, 2004.

[HWM04]

Helbing, Rene P., Walker, Richard C., Mertz, Pierre, Bronson, Barry, Nishimura, Ken A., Personal viewing device with system for providing identification information to a connected system, United States Patent (20) #6735328. May 11, 2004.

[HFW04]

Ho, Peter, Graham M. Flower, Richard C. Walker, Multiplexer with channel sectioning, selectively actuated current sources, and common-base amplifiers, United States Patent (21) #6760349, July 6, 2004.

[SNW04]

Seet, Adrian Wan-Chew, Ken Nishimura, Richard C. Walker, Adaptive decoder for skin effect limited signals, United States Patent (22) #6760551, July 6, 2004.

[WBN04]

Walker, Richard C., Travis N. Blalock, Neela B. Gaddis, Electro-optical material-based grey scale generating method , United States Patent (23) #6795064, September 21, 2004.

[WaT05]

Walker, Richard C., Patricia A. Thaler, Data communication system with self-test facility, United States Patent (24) #6862701, March 1, 2005.

[WMT05]

Walker, Richard C., Pierre H. Mertz, Barclay J. Tullis, Immersive Display System, United States Patent (25) #6870520, March 22, 2005.

[WAM05]

Walker, Richard C., Bharadwaj Amrutur, Peter Mottishaw, Steven C. Joiner, Larry A. Chesler, Ian Hardcastle, Network monitoring system with built-in monitoring data gathering, United States Patent (26) #6975617, December 13, 2005.